The present invention pertains to a system and method for calibrating testers used to test electronic components such as semiconductor devices.
Following fabrication and packaging, semiconductor devices are tested to ensure they operate as intended and to quantify various critical operating parameters, e.g., access time. Based on this testing, the devices are then sorted into various categories as a function of their operating characteristics, with the higher performing devices selling for more than lower performing devices.
Semiconductor chip testers are routinely calibrated and offsets are provided as a result of such calibration to ensure that test measurements are as accurate as possible. Unfortunately, known tester calibration techniques do not adequately address the behavior of tester receivers, cabling, fixturing, contactors and other elements xe2x80x9cdownstreamxe2x80x9d of the tester driver, with the result that tester offsets, which account for introduced element delays, cannot be accurately determined.
To ensure devices falling within a given sort category meet the performance requirements for that category, it is necessary to provide a guardband to account for the full extent of delay potentially introduced by the fixturing, product contactors and other elements. Thus, for example, for a chip having a target access time of 1,000 picoseconds, it may be necessary to reject all devices having a measured access time of 900 picoseconds and slower, with the difference between these two values being the guardband. If the guardband can be reduced, some of the devices falling into a lower sort category will necessarily fall in a higher sort category, resulting in an increased total chip revenue.
Known tester calibration techniques only indirectly address tester fixture delay, and additionally suffer from other drawbacks. One technique involves the use of a known good part having carefully quantified operating parameters, i.e., a xe2x80x9cgolden device.xe2x80x9d By subtracting known delay in the golden device from delays otherwise introduced by the tester, offsets accounting for such delays can be generated and used in testing future products. Unfortunately, because the golden device is active, its operating parameters change slightly with changes in temperature, voltages applied, and other factors, arising from operation. To account for this variability, guardbands must be applied to the known delay of the golden device, thereby giving rise to the test yield problems referenced above.
Other known calibration techniques use programmable, active delays. Typically, such techniques involve the use of a relay matrix that switches an active delay element between tester channels. In addition to the cumbersome fixturing associated with the use of this calibration technique, and a lengthy calibration time, e.g. three to four hours, the relays in the matrix introduce delay which must also be accounted for by guardbanding.
U.S. Pat. No. 5,256,964 to Ahmed et al. (xe2x80x9cthe ""964 patentxe2x80x9d), describes the use of active delay elements in connection with tester calibration. While the method and system of the ""964 patent is believed to constitute an advance in the art, it suffers from some of the problems associated with active known delay elements that are discussed above.
One aspect of the present invention is a method of calibrating a tester used to test an electronic component, the tester having a driver, a receiver channel, and an interface for connecting the driver and the receiver channel to the electronic component. A first step in the method comprises providing a passive calibration module having an electrical path with a known delay. Next, the calibration module is connected with the interface so that a test signal may be provided to the calibration module via the driver and carried by the electrical path to the receiver channel. Finally, the test signal is provided via the driver at t0.
Another aspect of the present invention is a method of calibrating tester receiver channels before testing electronic components. The method includes the steps of providing a tester for testing electronic components, the tester having a plurality of receiver channels, and providing a test signal having a known characteristic to at least one of the receiver channels. Then, a measurement of the known characteristic is performed and the receiver is calibrated by comparing the known characteristic with the measurement of the characteristic. Finally, an offset is created based on a difference between the known characteristic and the measurement.
Still another aspect of the invention is a tester calibration system for testing a DUT (device under test) having a reference clock contact and a plurality of data output contacts. The system comprises a tester and a socket for receiving a DUT, the socket being connected to the tester and having a plurality of contactors for making electrical contact with the reference clock contact and the plurality of data output contacts of the DUT. The system also includes a plurality of calibration modules, each having a first contact, a second contact and a transmission line with a known delay connected between the first contact and the second contact. Each of the plurality of calibration modules (i) is sized for receipt in the socket, (ii) has said first contact positioned to contact the contactor that contacts the reference clock contact of the DUT and (iii) has the second contact positioned to contact a corresponding respective one of the contactors that is different than ones of the contactors that the second contacts on others of the plurality of calibrations modules contact.